Today I learned how to manually calculate SPU operation dual issue rate. One of documents SPU document explained it very well.
There are two different types of operations: Even and Odd. When Even operation and Odd operation are fetched together they can be dual-issued. Each operation consists of 4bytes and OPCODE is most of time significant 11bits; the PDF document has list of instructions with their OPCODEs.
There is an important alignment limitation. When Even operations are stored in odd memory address or Odd operations are stored in even memory address, they cannot be dual-issued. Here the term, Even address means, any address value whose 3rd bits from LSB is zero; one for Odd address. For example, 0xXXX0, 0xXXX1, 0xXXX2 and 0xXXX3 belong to Even address.
Each operation size is 4byte and instruction fetching occurs for each 8bytes. For example, address from 0xXXX0 to 0xXXX7 will be fetched at once and address from 0xXXX8 to 0xXXXF will be fetched next.
When Even operation is stored at Odd address, 0xXXX4~0xXXX7 or 0xXXXC~0xXXXF, it will prevent the fetched instructions from being dual issued. Likewise, when Odd operation is stored at even adress, 0xXXX0~0xXXX3 or 0xXXX8~0xXXXB, it will prevent too. Whenever dual-issuing fails, one of pipeline units stalls.
I remember reading the same thing from one of articles in the book, "GPU pro". But I have almost forgotten it.